An asynchronous power aware and adaptive NoC based circuit
| dc.contributor.author | Beigné, Edith | |
| dc.contributor.author | Clermidy, Fabien | |
| dc.contributor.author | Lhermet, Helene | |
| dc.contributor.author | Miermont, Sylvain | |
| dc.contributor.author | Thonnart, Yvain | |
| dc.contributor.author | Tran, Xuan Tu | |
| dc.contributor.author | Valentian, Alexandre | |
| dc.contributor.author | Varreau, Didier | |
| dc.contributor.author | Vivet, Pascal | |
| dc.contributor.author | Popon, Xavier | |
| dc.contributor.author | Lebreton, Hugo | |
| dc.date.accessioned | 2016-11-29T06:18:16Z | |
| dc.date.available | 2016-11-29T06:18:16Z | |
| dc.date.issued | 2009-04 | |
| dc.identifier.uri | http://ds.libol.fpt.edu.vn/handle/123456789/2013 | |
| dc.description | 10 pages | en_US |
| dc.description.abstract | Abstract—In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. A fully power-aware globally- asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an asynchronous network-on-chip providing scalable communication and a 17 Gb/s ... | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | Network-on-a-chip | en_US |
| dc.subject | Circuits | en_US |
| dc.subject | Energy consumption | en_US |
| dc.subject | Throughput | en_US |
| dc.subject | Voltage control | en_US |
| dc.subject | Communication system control | en_US |
| dc.subject | Dynamic voltage scaling | en_US |
| dc.subject | Frequency | en_US |
| dc.subject | Power control | en_US |
| dc.subject | Delay | en_US |
| dc.title | An asynchronous power aware and adaptive NoC based circuit | en_US |
| dc.type | Other | en_US |
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