Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip
| dc.contributor.author | Pham, Thi Hong | |
| dc.contributor.author | Pham, Phi Hung | |
| dc.contributor.author | Tran, Xuan Tu | |
| dc.contributor.author | Kim, Chulwoo | |
| dc.date.accessioned | 2016-11-29T08:17:06Z | |
| dc.date.available | 2016-11-29T08:17:06Z | |
| dc.date.issued | 2008-06-04 | |
| dc.identifier.uri | http://ds.libol.fpt.edu.vn/handle/123456789/2052 | |
| dc.description | 4 pages | en_US |
| dc.description.abstract | Abstract—VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characterization of onchip traffics and traffic-performance evaluation are necessary steps bringing comprehensive and effective NoC design. This paper presents an analysis and performance evaluation framework of backtracked routing Network-on-Chip that provides guaranteed and energy-efficient data ... | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | 2008/6/4 | en_US |
| dc.subject | Network-on-Chip | en_US |
| dc.subject | On-chip traffics | en_US |
| dc.subject | On-chip communication | en_US |
| dc.subject | Network architecture | en_US |
| dc.subject | Performance evaluation | en_US |
| dc.title | Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip | en_US |
| dc.type | Working Paper | en_US |
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