Soft-error resilient 3D Network-on-Chip router
| dc.contributor.author | Dang, Khanh N | |
| dc.contributor.author | Meyer, Michael | |
| dc.contributor.author | Okuyama, Yuichi | |
| dc.contributor.author | Abdallah, Abderazek Ben | |
| dc.contributor.author | Tran, Xuan Tu | |
| dc.date.accessioned | 2016-11-29T08:31:27Z | |
| dc.date.available | 2016-11-29T08:31:27Z | |
| dc.date.issued | 2015-09-22 | |
| dc.identifier.uri | http://ds.libol.fpt.edu.vn/handle/123456789/2056 | |
| dc.description | 6 pages | en_US |
| dc.description.abstract | Abstract—Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors, or soft errors, have severe consequences on chip performance, such as deadlock, data corruption, packet loss and increased packet ... | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | Pipelines | en_US |
| dc.subject | Computer architecture | en_US |
| dc.subject | Ports (Computers) | en_US |
| dc.subject | Transient analysis | en_US |
| dc.subject | Switches | en_US |
| dc.subject | Power demand | en_US |
| dc.subject | Error analysis | en_US |
| dc.title | Soft-error resilient 3D Network-on-Chip router | en_US |
| dc.type | Working Paper | en_US |
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