An asynchronous low-power innovative network-On-chip including design-for-test capabilities
| dc.contributor.author | Thonnart, Yvain | |
| dc.contributor.author | Tran, Xuan Tu | |
| dc.contributor.author | Vivet, Pascal | |
| dc.contributor.author | Beigne, Edith | |
| dc.contributor.author | Clermidy, Fabien | |
| dc.contributor.author | Durupt, Jean | |
| dc.date.accessioned | 2016-11-29T12:44:10Z | |
| dc.date.available | 2016-11-29T12:44:10Z | |
| dc.date.issued | 2009-10-12 | |
| dc.identifier.uri | http://ds.libol.fpt.edu.vn/handle/123456789/2067 | |
| dc.description | 3 pages | en_US |
| dc.description.abstract | Abstract The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot be satisfied only by point-to-point or shared-bus interconnects. By providing more bandwidth at reasonable power consumption, new communication infrastructures like NoCs seem promising, but are still limited by implementation issues. We present in this paper an Asynchronous Network-on-Chip architecture with two main innovations. Firstly, an automatic power regulation scheme is proposed to dynamically ... | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | Network-on-a-chip | en_US |
| dc.subject | Design for testability | en_US |
| dc.subject | Power system interconnection | en_US |
| dc.subject | Energy consumption | en_US |
| dc.subject | Logic testing | en_US |
| dc.subject | CMOS technology | en_US |
| dc.subject | Delay | en_US |
| dc.subject | System-on-a-chip | en_US |
| dc.subject | Bandwidth | en_US |
| dc.subject | Technological innovation | en_US |
| dc.title | An asynchronous low-power innovative network-On-chip including design-for-test capabilities | en_US |
| dc.type | Working Paper | en_US |
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