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FPT University|e-Resources > Bài báo khoa học (Scientific Articles) > Articles published by FPT lecturers >
Please use this identifier to cite or link to this item: http://ds.libol.fpt.edu.vn/handle/123456789/2047

Title: Simulation and performance evaluation of a network-on-chip architecture based on SystemC
Authors: Le Van, Thanh Vu
Tran, Xuan Tu
Ngo, Dien Tap
Keywords: Throughput
IP networks
Load modeling
Adaptation models
Routing
Computer architecture
Data models
Issue Date: 10-Oct-2012
Publisher: IEEE
Abstract: Abstract—The Network-on-Chip (NoC) paradigm has been recently known as a competitive on-chip communication solution for large complex systems such as multi-core and/or manycore systems thanks to its advantages. However, one of the main challenging issues for NoC designers is that the network performance should be rapidly and early pre-proved for target applications.
Description: 5 pages
URI: http://ds.libol.fpt.edu.vn/handle/123456789/2047
Appears in Collections:Articles published by FPT lecturers

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