The Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the
on chip communication in the next SoC generation, especially, asynchronous NoCs. One of
the challenges for asynchronous NoC-based systems design is testing asynchronous
network architectures for manufacturing defects. To improve the testability of asynchronous
NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT)
architecture. In this architecture, each asynchronous network node is surrounded by an ...