A novel asynchronous first-in-first-out adapting to multi-synchronous network-on-chips

Abstract

Abstract—The integration of a variety of IP cores into a sin-gle chip to meet the high demand of new applications leads to many challenges in timing issues, especially the interface between different clock domains. Globally Asynchronous, Locally Synchronous (GALS) approach addresses these challenges by dividing a chip into several independent subsystems working with different clock signals. In multi-synchronous Network-on-Chip (NoC) based on GALS architecture, the network routers run with different frequencies, so ...