High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router

Abstract

In this paper, we present a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high-level design using SystemC. The RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port–named Routing Modification port–into the conventional router architecture, the network router is able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to ...