Design and Implementation of a SoPC System for Speech Recognition

Abstract

Abstract This paper presents the design of a System on Programmable Chip (SoPC) based on Field Programmable Gate Array (FPGA) for speech recognition in which Mel-Frequency Cepstral Coefficients (MFCC) for speech feature extraction and Vector Quantization (VQ) for recognition are used. The execution speed of the blocks in the speech recognition system is surveyed by calculating the number of clock cycles while executing each block.