Network-on-Chips: Design and Test Challenges in Nanoscale Era

Abstract

Nowadays, more and more complex intellectual property (IP) cores communicating with each other has been intently integrated into a system to meet the high demand of new applications. This make the on-chip communication become a critical issue and the conventional bus based communication using a single bus or a hierarchy of busses could not response to the communication requirements between the integrated IP cores because of their poor scalability with system size, their shared bandwidth between all the integrated ...