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FPT University|e-Resources > Bài báo khoa học (Scientific Articles) > Articles published by FPT lecturers >
Please use this identifier to cite or link to this item: http://ds.libol.fpt.edu.vn/handle/123456789/2082

Title: Network-on-Chips: Design and Test Challenges in Nanoscale Era
Authors: Tran, Xuan Tu
Keywords: Network-on-Chip (NoC)
On-chip communication
Design and test challenges
JPEG encoder
Issue Date: 8-Aug-2011
Series/Report no.: IEICE Catalog Number;C3055
Abstract: Nowadays, more and more complex intellectual property (IP) cores communicating with each other has been intently integrated into a system to meet the high demand of new applications. This make the on-chip communication become a critical issue and the conventional bus based communication using a single bus or a hierarchy of busses could not response to the communication requirements between the integrated IP cores because of their poor scalability with system size, their shared bandwidth between all the integrated ...
Description: 9 pages
URI: http://ds.libol.fpt.edu.vn/handle/123456789/2082
ISSN: 978-4-88552-258-1
Appears in Collections:Articles published by FPT lecturers

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